1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
Most of currently available semiconductor integrated circuits are constructed as an IC package. System performance of some semiconductor integrated circuits mounted on the IC package depends on its storage capacity. Preferably, such semiconductor integrated circuits are designed to have the same packaging specification and memory function and variable storage capacity so that they can be mounted on a same substrate. Thus, a semiconductor integrated circuit enabling the storage capacity of a system to be changed depending on demanded system performance is constituted.
As a technology for constituting semiconductor integrated circuits having semiconductor chips with the same packaging specification and memory function and different storage capacity, a technology for stacking and mounting a plurality of semiconductor chips in one package is known. Such a technology has been applied, for example, to a case in which large storage capacity is intended by stacking a plurality of semiconductor memory chips.
In some semiconductor integrated circuits in which a plurality of semiconductor chips are stacked, terminals of a package for sending/receiving an input signal such as an address signal or a control signal are shared among a plurality of the chips. Moreover, in some of them, an I/O terminal for inputting/outputting data is shared among a plurality of the semiconductor chips. When the I/O terminal is shared, it is preferable that reading/writing of data is performed for a desired chip by selecting each of the chips separately. In such a case, each of the chips is selected by using a chip selection signal which is generally referred to as a chip enable signal/CE. A technology regarding a semiconductor integrated circuit has been known, in which a chip enable terminal is shared among a plurality of chips and each of the chips can be selected by an address signal (refer to, for example, Japanese Patent Laid-Open No. 2003-7963 and Japanese Patent Laid-Open No. 2006-172700).
In Japanese Patent Laid-Open No. 2003-7963, a technology regarding a multi-chip stack type semiconductor memory device is disclosed, in which a chip enable terminal is shared by a plurality of chips and each of chips can be selected by an address signal. FIG. 1 is a block diagram illustrating the configuration of a semiconductor device described in Japanese Patent Laid-Open No. 2003-7963. In the semiconductor device described in Japanese Patent Laid-Open No. 2003-7963, memory chips 110A and 110B are stacked. As illustrated in FIG. 1, each of the memory chips 110A and 110B is constituted by including an memory array 111, an X decoder 112, a Y decoder 113, an address buffer 114, a sense amplifier & write-in circuit 115, an input/output circuit 116, a chip enable control circuit 117, an input buffer 118, a control circuit 119, and an address bits comparison circuit 120.
In the memory array 111, a plurality of memory cells arranged in a matrix are included. The X-decoder 112 decodes an input X-based address and causes one word line in the memory array 111 to be in a selection level. The Y decoder 113 decodes an input Y-based address and selects a corresponding bit line in the memory array 111. The address buffer 114 takes in the input X-based address and Y-based address and supplies them to the X decoder 112 and the Y decoder 113. The sense amplifier & write-in circuit 115 amplifies a signal read out in the selected bit line or provides the electric potential to the bit line to the signal depending on write-in data. The input/output circuit 116 outputs the read-out data or takes in the write-in data from outside the chip. The chip enable control circuit 117 takes in a chip enable signal/CE input from the outside of the chip to generate an internal control signal. The input buffer 118 takes in external control signals such as a write enable signal/WE, a reset signal RES, and an out enable signal/OE. The control circuit 119 generates a control signal of the inside of the chip depending on a taken-in control signal to control the inside.
The semiconductor chips 110A and 110B described in Japanese Patent Laid-Open No. 2003-7963 are provided with a chip address CAD, respectively. The address bits comparison circuit 120 causes the chip enable control circuit 117 to be enabled depending on the electric potential applied to the chip address CAD and the most significant bit of a plurality of the address signals supplied from the outside of the chip. For example, the address bits comparison circuit 120 causes the chip enable control circuit 117 to be enabled depending on the most significant bit A22 of address signals A0 to A22 (such as 23 bits), and the electric potential applied to the chip address CAD. One of the chip address CAD of the semiconductor chip 110A and the chip address CAD of the semiconductor chip 110B is connected to a first power-supply-voltage terminal VCC of the package and the other of them is connected to a second power-supply-voltage terminal VSS of the package.
FIG. 2A is a circuit diagram illustrating the configuration of the chip enable control circuit 117 and the address bits comparison circuit 120. The chip enable control circuit 117 is constituted by including an AND gate G1, an inverter G2, and a NAND gate G3. The AND gate G1 uses the chip enable signal/CE, and the reset signal RES as the input thereof. The inverter G2 reverses the output of the AND gate G1, and supplies it to the address bits comparison circuit 120. The NAND gate G3 generates an internal chip enable signal CEB based on the output signal of the AND gate G1, and the signal from the address bits comparison circuit 120.
The address bits comparison circuit 120 is constituted by including a first NOR gate G11, a second inverter G12, an Exclusive-OR gate 13, and a third inverter G14. The first NOR gate G11 uses the output signal and the address most significant bit A22 of the inverter G2 of the chip enable control circuit 117 as the input thereof. The second inverter G12 generates a signal corresponding to the electric potential applied to the chip address CAD. The Exclusive-OR gate G13 uses the output signals of the second inverter G12 and the first NOR gate G11 as the inputs thereof. The third inverter G14 reverses the output of the Exclusive-OR gate G13, and supplies it to the NAND gate G3 of the chip enable control circuit 117. FIG. 2B is a circuit diagram illustrating another configuration of the chip enable control circuit 117 and the address bits comparison circuit 120. As illustrated in FIG. 2B, the circuit having the other configuration is provided with an selector SEL, instead of the Exclusive-OR gate G13, and constituted so as to control the selector SEL with the output of the second inverter G12 which generates a signal depending on the electric potential applied to the chip address CAD. These circuits causes the internal chip enable signal CEB to be in a chip selection state or a non selection state, depending on the electric potential applied to the address most significant bit A22 and the chip address CAD.
In the technology described in Japanese Patent Laid-Open No. 2003-7963, the chip address CAD is input into the chip address data comparison circuit 120 connected to an extension address (A24). The address bits comparison circuit 120 compares the chip address CAD and the address most significant bit A22, and determines to select the chip address CAD if they coincide with each other and determines not to select the chip address CAD if they do not coincide with each other. More specifically, when the chip address CAD has the same electric potential as that of the second power supply voltage VCC, the chip address data comparison circuit 120 will have a positive chip enable function, and when the chip address CAD has the same electric potential as that of the first power supply voltage VSS, the chip address data comparison circuit 120 will have a negative chip enable function. When chips are stacked together, by changing levels given to the chip address CAD in each of the upper and lower chips, the two memory chips are operated as one memory chip having two times of storage capacity.
Moreover, in Japanese Patent Laid-Open No. 2006-172700, a technology regarding a low electric power multi-chip semiconductor memory device and a chip enable method thereof are disclosed. FIG. 3 is a circuit diagram illustrating the configuration of a chip enable buffer 150 of the semiconductor memory device described in Japanese Patent Laid-Open No. 2006-172700. The chip enable buffer 150 is constituted by including a chip selection section 151 and a signal generation section 157. The chip selection section 151 compares an address A24 input from outside and identification information FCS of chips. After that, in response to the comparison result and mode information of two semiconductor chips, the chip selection section 151 selects one of the semiconductor chips 1. The signal generation section 157, in response to a chip enable signal input from outside, generates an internal chip enable signal nCE1 or nCE2 activated by the selected chip.
Further, other than the above mentioned related technologies, a technology regarding a chip selection terminal provided for selecting any chip among a plurality of semiconductor element chips has been known (refer to, for example, Japanese Patent Laid-Open No. 05-210577). In Japanese Patent Laid-Open No. 05-210577, an internal logic designation circuit in which each one of a pair of chip selection terminals (cs/cs, in Japanese Patent Laid-Open No. 05-210577) has a complementary logic value, is constituted at the time of designing semiconductor element chips. In addition, a technology for connecting only one of a pair of the chip selection terminals to an external input end, is described.
As illustrated in FIG. 2A or FIG. 2B, in the technology described in Japanese Patent Laid-Open No. 2003-7963, in order to compare the levels of the most significant bit A22 and the chip address CAD, the address bits comparison circuit 120 is provided with an EX-OR or a selector (SEL). Therefore, the circuit configuration of the address bits comparison circuit 120 becomes complicated, and circuit delay time also becomes large. Moreover, as illustrated in FIG. 3, the technology described in Japanese Patent Laid-Open No. 2006-172700, the extension address (A24) and the EX-OR of a chip identification signal (FCS) are provided as chip enable buffer. Therefore, the circuit configuration of the chip enable buffer 150 becomes complicated, and circuit delay time also becomes large.
Moreover, in the technology described in Japanese Patent Laid-Open No. 05-210577, an input pad is clamped to VCC or GND inside a chip. Therefore, in a pair of positive and negative chip selection terminals, the positive chip selection terminal is clamped to VDD and the negative chip selection terminal is clamped to GND. Therefore, when an input is caused to be in a standby state, pin leak may flow.
Moreover, for a general purpose memory if it is a low storage capacity product requiring no pin, the extension address pin is defined as an NC pin. When the memory chip described in Japanese Patent Laid-Open No. 2003-7963 or Japanese Patent Laid-Open No. 2006-172700 is assembled with one chip, in order to hide the function of an extension address, it is necessary to connect both of the address most significant bit A22 and the chip address CAD to VSS or VCC. Therefore, for the memory chip described in Japanese Patent Laid-Open No. 2003-7963 or Japanese Patent Laid-Open No. 2006-172700, when it is assembled into a one-chip configuration package using a lead frame, the pin to be the expansion address will not be in an NC (no connection) state, but have the first power supply voltage VSS or the second power supply voltage VCC. By this, in some cases, the compatibility of the IC package may be lost.
Hereinafter, using reference numerals used in [DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS], means for solving problems will be described. These numbers are given for clarifying the correspondence relationship between the description in [What is claimed is:] and the description in [DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS]. However, these numbers may not be used for interpretation of the technical scope of the invention described in [What is claimed is:].